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Unpacking AI Inference: Batching, Sparsity, and the Memory Wall

Ever wondered why some AI models are faster but more expensive, or how architectural choices fundamentally shape AI’s progress? This deep dive reveals the complex interplay between hardware, software, and fundamental architectural decisions that dictate the real-world performance, cost, and ultimate scalability of large language models. From the granular economics of batching to the physical constraints of rack design, understanding these elements is key to grasping the current state and future trajectory of AI.

Core Question: How do architectural decisions in AI infrastructure impact the latency, cost, and ultimate scalability of large language models?

Highlights

• Batch size is the primary lever for trading latency for cost efficiency in AI inference, dramatically amortizing fixed overheads.
• Roofline analysis, considering memory bandwidth and compute performance, reveals bottlenecks in transformer model execution, often shifting between compute-bound and memory-bound states.
• Sparse Mixture-of-Experts (MoE) models can significantly reduce compute by activating fewer parameters but demand larger batch sizes and increased memory capacity, pushing hardware to its limits.
• Physical rack design and inter-rack communication bandwidth heavily constrain the practical scalability of MoE layers and dictate optimal model distribution strategies.
• Pipelining can optimize memory capacity usage for model weights during inference but offers less benefit for the KV cache, which remains a significant memory and bandwidth challenge.
• API pricing structures for LLMs often reflect underlying hardware costs and bottlenecks, offering insights into memory tiers, context length trade-offs, and prefill vs. decode expenses.

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The Core Mechanics of AI Inference: Latency and Cost Trade-offs

Batching for Efficiency

The underlying mechanics of AI inference in a cluster reveal why the field’s architectures and pricing models are structured as they are. Understanding how training and inference processes operate on a cluster provides crucial insights into the fundamental reasons behind AI’s current trajectory and progress. This discussion, presented as a blackboard lecture, aims to demystify these complex interactions.

A common scenario in commercial AI is the offering of a “Fast Mode”—where, for six times the price, users get tokens 2.5 times faster. Conversely, one might ask if a “Slow Mode” could offer significantly cheaper prices for those willing to endure longer wait times. The immediate, overarching factor at play here is the batch size, which we will quantify to understand its precise implications on latency and cost.

Our analysis begins with a “roofline analysis” of transformer models running on a cluster of chips, specifically a Blackwell NVL72 rack equipped with 72 GPUs. This approach examines the limits imposed by memory bandwidth and compute performance. Additionally, we will simplify the model to focus on two core factors: the time required to operate on the model’s weights and the time needed to manage the Key-Value (KV) cache.

Estimating inference time involves considering both memory fetches and computational throughput. While precise prediction is challenging, we can approximate that the total time must be greater than or equal to the sum of these two components. Even this simplified model offers strong predictive power regarding system performance.

Regarding compute time, two primary operations are involved: multiplying by all active parameters and performing attention computations. The dominant factor is the multiplication by active parameters, which scales directly with the batch size and the number of active parameters, divided by the chip’s computational throughput (FLOPs). While attention computation also requires compute, it is generally much smaller in comparison and often ignored for this high-level analysis.

It is crucial to clarify that “batch” in this context does not mean serving a single user at a time. Instead, it refers to concurrently serving multiple different users or requests. Batching is a highly favorable optimization because, without it, the economic cost of inference can be thousands of times worse.

For instance, the DeepSeek V3 model, while having 700 billion total parameters, only uses about 37 billion active parameters for a single AI token. Our modeling of compute performance focuses on these active parameters. These time estimates always represent a lower bound, as additional terms might be ignored for simplicity.

On the memory side, operations involve fetching all model weights—the total number of parameters, not just the active ones. Furthermore, there’s the KV cache fetch time, which directly depends on the batch size, the context length (number of tokens), and the bytes per token. This KV cache is a critical model parameter.

To explain the KV cache simply: during the autoregressive decoding process, when a model generates a new token, it needs to consider all previously generated tokens. The model doesn’t recompute these past tokens from scratch every time; instead, it stores an internal representation of them, known as the KV cache. This process of the new token attending to the history of tokens is largely dominated by memory fetches rather than matrix multiplications, as indicated by the memory bandwidth calculation. These fundamental equations allow us to analyze the sensitivity of performance to batch size and, separately, to context length.

Latency vs. Cost Dynamics

When plotting latency against batch size, the shape of the curve initially shows a weak dependence on batch size before becoming linear. This demonstrates an inherent lower bound on latency for any given hardware configuration, primarily because reading all total model parameters from memory into the chips takes a fixed amount of time, regardless of how small the batch is.

The relative slopes of the compute time and KV cache growth are critical. If compute time dominates, the system is compute-limited; if memory time dominates, it’s memory-limited. Crucially, the context length significantly influences this balance. As context length increases, KV cache fetch time grows, potentially shifting the bottleneck from compute-limited to memory-limited.

A highly desirable operating point is when the system is equally memory-bound and compute-bound, representing an optimal balance. Deviating significantly from this “Goldilocks zone” can drastically impact machine utilization efficiency. For example, a non-optimal context length can reduce machine utilization by half.

It’s worth noting that dense attention mechanisms result in memory fetches that scale linearly with context length. However, sparse attention, as implemented in some models like DeepSeek, can offer a significant improvement by causing this term to scale with the square root of context length, making it much more efficient for very long contexts.

While latency is important, the true economic measure is cost per token. This is derived by dividing the total inference time by the number of processed tokens (batch size). The previously linear compute curve now becomes a constant when divided by batch size. Similarly, the linear KV fetch curve also becomes constant. The constant weight fetch component, however, transforms into a hyperbola (1/B) when divided by batch size.

This cost analysis reveals a characteristic shape: cost per token starts very high for small batch sizes (e.g., batch size one) due to unamortized weight fetches. As batch size increases, these fixed costs are amortized over more elements, causing the cost to drop sharply. Eventually, the system becomes compute-bound, establishing a limiting lower bound on cost. This is the sweet spot for “Slow Mode” scenarios, where users are willing to wait for maximum cost efficiency.

Solving for the optimal batch size—when memory time equals compute time—reveals a surprisingly stable result. Ignoring the KV cache for simplicity, the optimal batch size is approximately 300 times the sparsity factor (ratio of total to active parameters). For a model like DeepSeek, with a sparsity of around 8, this suggests an optimal batch size of roughly 2,000.

This means a typical batch size of about 2,000 unique sequences is needed to achieve peak efficiency for a single forward pass. In practice, companies might aim for slightly larger batches to account for real-world inefficiencies. This batch size implies a “train schedule” for GPUs: a new batch departs every fixed interval, often around 20 milliseconds, regardless of whether it’s full.

This 20-millisecond interval is not arbitrary; it’s often derived from the time it takes to read the entire High-Bandwidth Memory (HBM) capacity of a chip. For example, a Rubin GPU’s 288 GB HBM with 20 TB/s bandwidth translates to approximately 15 milliseconds to “evacuate” and replace its HBM. This sets a fundamental limit on how quickly a GPU can process memory-intensive tasks.

💡 Digging Deeper

Q: What is “roofline analysis” in the context of AI inference?
A: Roofline analysis is a method to identify whether a system’s performance is limited by memory bandwidth (how fast data can be moved) or computational throughput (how many operations can be performed). It helps pinpoint bottlenecks by comparing actual performance to theoretical hardware limits.

Q: How does the KV cache impact memory performance, especially with increasing context length?
A: The KV cache stores internal representations of past tokens for attention mechanisms. As context length increases, the size of the KV cache grows, leading to more memory fetches and potentially making the system memory-bandwidth bound.

Q: Why does batching dramatically reduce cost per token, but not necessarily latency?
A: Batching amortizes the fixed cost of loading model weights and other overheads across multiple concurrent requests. This reduces the cost per token but doesn’t necessarily decrease the latency for a single request, as it still has to wait for its turn in a full batch.

Scaling Models: Sparsity, Hardware, and Communication Bottlenecks

The Economics of Sparsity

The optimal batch size, around 2,000, is primarily dictated by the model’s sparsity, not its overall size. This is a very interesting result because it implies that, beyond a certain point, merely scaling up model size doesn’t change the fundamental efficiency of processing individual tokens; sparsity becomes the key knob. This also means that more sparsity translates directly to a need for less compute.

Converting this batch size to a more tangible metric, a system processing 2,000 tokens in a 15-millisecond interval (the HBM drain time) can achieve approximately 128,000 tokens per second. To put this in perspective, some frontier models have announced global traffic in the hundreds of millions of tokens per second. This 128,000 tokens/second represents a significant fraction, roughly one-thousandth, of such global traffic, indicating a substantial capacity for a single system.

A critical question then arises: how far can sparsity be pushed? As the sparsity ratio increases (fewer active parameters relative to total parameters), does the model’s quality degrade faster than the compute savings? This is an empirical question concerning model quality, not easily solvable analytically, and depends heavily on the specific Mixture-of-Experts (MoE) implementation.

Historically, research into MoE models, such as those discussed in “Unified Scaling Laws for Routed Language Models,” explored this trade-off. These studies sometimes showed that for a fixed number of active parameters, increasing the number of experts (and thus sparsity) could lead to an improvement in model quality. For example, a 64-expert model with 370 million active parameters might achieve the same quality as a dense 1.3 billion parameter model.

However, the returns on increasing sparsity are not always linear. A huge increase in total parameter count (e.g., 64x) might only yield a modest increase in efficiency or quality (e.g., 4x). While sparsity offers a “pure win” from a compute efficiency standpoint—as long as you can run a large enough batch to amortize the increased memory fetches—it also significantly increases memory capacity consumption. This presents a trade-off: greater sparsity often requires more memory, meaning you might need to find more users to fill larger batches or tolerate higher costs.

MoE Layer Layout and Rack Architecture

A typical Mixture-of-Experts (MoE) layer consists of a router and numerous experts, usually standard Multi-Layer Perceptrons (MLPs). Incoming tokens pass through the router, which decides to route them to a small fraction of these experts—perhaps 1 in 32. After processing, the outputs from these activated experts are summed.

The most effective strategy for deploying MoE layers is expert parallelism, where different experts are placed on different GPUs. For instance, a DeepSeek model with 256 experts might be distributed across 64 GPUs, leading to about four experts per GPU (or two per GPU in simplified diagrams). This distributed layout creates a unique communication challenge.

The communication pattern for an MoE layer is inherently “all-to-all.” Any GPU might need to communicate with any other GPU depending on the router’s decisions. Modern rack architectures, such as Nvidia’s Blackwell, are explicitly designed to facilitate this. They place GPUs on the outside of the rack, connected to internal NV switches via high-speed NVLink connections. This “scale-up” network allows any GPU to communicate with any other within the rack in just two hops (GPU -> switch -> GPU).

However, the major bottleneck appears when trying to scale MoE layers across multiple racks. Communication between racks, using a “scale-out” network, is typically much slower—around eight times slower—than intra-rack NVLink. If an MoE layer spans two racks, roughly half of the tokens will need to travel between racks, dramatically impacting performance due to this slower inter-rack communication.

A rack is a standard physical unit in data centers, typically a few meters tall and a meter or two wide, housing approximately 64 GPUs or other XPUs. Its size is constrained by physical limitations like power delivery, weight, and cooling capacity. While data centers contain thousands of these racks, the internal communication within a rack is fundamentally different from external communication.

This hierarchy of communication—fast scale-up within a rack, slower scale-out between racks—means that a single rack often acts as the effective boundary for an MoE layer. Advances in hardware, moving from Hopper (8 GPUs) to Blackwell (72 GPUs) and projected Rubin (500+ GPUs), are driven by the need to create larger “interconnect domains” or scale-up networks. This expansion is not merely a product decision but a result of overcoming significant engineering challenges related to cabling density, physical space, and the bend radius of high-speed cables within the increasingly dense racks.

💡 Digging Deeper

Q: What are the primary physical constraints limiting the size and density of a modern AI rack?
A: The main constraints are power delivery, the overall weight of the rack, and the ability to effectively cool the densely packed components. Physical space for cabling and connector density also play a significant role.

Q: How does the “all-to-all” communication pattern of MoE layers interact with rack architecture?
A: MoE layers require any expert to potentially communicate with any other, leading to an all-to-all pattern. Rack architectures optimized with fast intra-rack interconnects (like NVLink) support this well, but communication becomes a bottleneck when experts are spread across racks due to slower inter-rack connections.

Q: What is the “scale-up network” versus the “scale-out network”?
A: The scale-up network refers to the high-bandwidth, low-latency connections within a single compute unit (like an Nvidia rack), designed for close-proximity communication (e.g., NVLink). The scale-out network refers to the slower, longer-distance connections between such units or to broader data center infrastructure.

Pipelining, Memory Tiers, and Advanced Cost Optimization

Pipelining Parallelism and Micro-Batching

The deployment of larger scale-up domains, like Nvidia’s Blackwell, represents a significant leap in model scaling capabilities. This aligns with approaches seen in Google’s TPU deployments, which have long featured very large scale-up domains, potentially contributing to the success of models like Gemini in terms of efficient pre-training.

While expert parallelism is well-suited for single-rack deployments due to its all-to-all communication pattern, other parallelism strategies are better designed for multi-rack environments. Data parallelism and pipeline parallelism are two such approaches. Pipeline parallelism, in particular, distributes different layers of a model across separate racks, allowing for scaling beyond the confines of a single interconnect domain.

The viability of pipeline parallelism depends on whether the communication bottleneck between racks (via the slower scale-out network) can be overcome by the gains from distributing the model. Typically, the scale-up network is about 8 times faster than the scale-out network. This speed difference must be balanced by the data expansion that occurs when tokens are routed to multiple activated experts across multiple layers. The implication is that model architecture often aligns with the physical topology, where layers map to racks or experts map to GPUs.

Pipelining, however, introduces the concept of “pipeline bubbles,” periods of idle time in the compute pipeline. During inference, these bubbles can be mitigated through micro-batching. Instead of waiting for one inference to complete all stages, subsequent inferences (micro-batches) are started immediately after the preceding one clears the first stage. This allows for continuous utilization of the pipeline.

In a training context, pipelining is more complex due to the need for a backward pass. A “hard stop” is often required at the end of the forward passes to accumulate gradients for an entire batch before the backward pass begins, leading to significant idle times. More sophisticated “zero-bubble” techniques exist to interleave forward and backward passes to improve efficiency.

For inference, pipeline parallelism doesn’t inherently improve latency or batch size for a single request. Instead, its primary benefit is reducing the memory capacity requirements per rack, as each rack only needs to store a fraction of the model’s weights. While useful, this benefit is less impactful if a single rack already has sufficient memory to hold the entire model, as is often the case with modern HBM capacities.

Memory Capacity, Bandwidth, and API Pricing

The total memory capacity demanded by a model is a sum of its total parameters (weights) and the KV cache, which grows linearly with batch size, context length, and bytes per token. Expert parallelism (E) distributes experts across GPUs, while pipeline parallelism (P) distributes layers across racks. While pipelining effectively reduces the weights memory footprint per GPU, it does not similarly reduce the KV cache memory footprint per GPU because the number of sequences in flight must increase to keep the pipeline busy.

This means that even if a model’s weights fit easily within a single rack, the KV cache can still become a limiting factor. However, larger scale-up domains are crucial for improving memory bandwidth, which directly translates to lower inference latency by speeding up the loading of weights and KV cache. This is why the increase in scale-up domain size from Hopper to Blackwell dramatically improves performance.

API pricing structures offer a fascinating window into these underlying hardware economics. For example, Gemini’s 50% price increase for context lengths over 200,000 tokens likely reflects the inflection point where memory bandwidth costs become dominant over compute costs. This transition occurs as the KV cache grows, making memory fetches the primary bottleneck.

A quick calculation suggests a bytes-per-token value of around 2 kilobytes at a 200,000 context length, which is plausible for models using dense attention with typical d-head and KV head configurations. This also hints at why extreme context lengths are not yet common: the memory bandwidth bottleneck is hard to overcome.

The significant price difference between processing input (prefill) and output (decode)—with decode often being 5x more expensive—further underscores the memory challenge. Decode is generally memory bandwidth-limited because it processes one token at a time, requiring frequent KV cache fetches. Prefill, by processing many tokens in parallel, can often be more compute-limited and thus cheaper per token.

Cache hits being significantly cheaper (e.g., 10x) highlights the trade-off between recomputing the KV cache from scratch (rematerialization) and storing it in various memory tiers. Rematerializing is essentially paying for GPU compute time. Storing, however, involves different costs based on the memory tier: HBM for speed, DDR for slightly slower but cheaper access, and flash or even spinning disk for much slower but far cheaper storage. These tiers are optimized for different “hold times.” For instance, API tiers offering cache for five minutes versus one hour might correspond to the drain times (capacity/bandwidth) of flash storage versus spinning disks, respectively, demonstrating how providers leverage a hierarchy of memory technologies to optimize costs based on data longevity requirements.

💡 Digging Deeper

Q: Why is pipelining less attractive for optimizing the KV cache compared to model weights?
A: While pipelining helps shard model weights across racks, the KV cache grows with the number of in-flight sequences and context length. The number of sequences in flight needs to increase to keep all pipeline stages busy, negating the memory savings for KV cache per GPU.

Q: How do the different API pricing tiers for cache hits (e.g., 5 minutes vs. 1 hour) relate to memory technology?
A: These tiers likely correspond to the “drain times” or effective retention costs of different memory technologies. Shorter durations might use faster, more expensive tiers like Flash storage, while longer durations could use slower, cheaper tiers like spinning disks.

Q: What is the primary bottleneck preventing current models from achieving context lengths in the millions of tokens?
A: The primary bottleneck is memory bandwidth and capacity, not compute. While sparse attention offers improvements, the fundamental limits of HBM and the empirical observation that context lengths have plateaued around 100-200K tokens suggest a cost-prohibitive barrier at extreme lengths.

AI Progress, Scaling Laws, and Cryptographic Analogies

Optimizing for Total Compute Cost

The historical stagnation in the total number of model parameters (beyond a trillion) until recently can be largely attributed to the lack of sufficiently large scale-up domains with adequate memory bandwidth. These domains are crucial for efficiently handling not only the model parameters themselves but also the burgeoning KV cache required for inference at scale. While pipeline parallelism offers a solution for distributing model weights, it’s the raw memory bandwidth of the entire scale-up domain that ultimately dictates latency and enables longer context lengths.

A general heuristic for minimizing the total cost of an AI system suggests that the costs associated with pre-training, Reinforcement Learning (RL), and inference should ideally be equalized. This rough equalization point tends to represent the most efficient allocation of compute resources across the model’s lifecycle.

Applying this heuristic, if we estimate real-world inference tokens at around 50 million per second for a model deployed for two months, this translates to approximately 200 trillion inference tokens. This figure aligns remarkably well with current rumors about the pre-training token counts for frontier models.

Such an alignment suggests that frontier models are currently “over-trained” by a factor of roughly 100 compared to what Chinchilla-optimal scaling laws would recommend for their active parameter count. This “over-training” likely reflects a strategic decision to optimize for total system cost, balancing the investment in pre-training with the long-term inference demands, and taking into account the probability of a model not reaching commercial viability.

Convergent Evolution: Neural Networks and Cryptography

Surprisingly, neural networks and cryptographic protocols exhibit a striking convergent evolution in their architectural patterns. Both fields grapple with the challenge of “mixing” or “scrambling” information across their inputs. Cryptographic hash functions, for instance, aim to make small input changes lead to drastically different, seemingly random outputs to ensure security. Neural networks, conversely, seek to extract meaningful, higher-level structure from often-garbled or unstructured inputs like text or biological sequences.

Despite these common high-level mechanisms, their ultimate goals are inverse. Cryptographic systems are designed to complexify information to prevent any meaningful interpretation, making them resistant to analysis. Neural networks, through gradient descent and careful architectural choices (like residual connections and LayerNorm), are optimized for interpretability of their derivatives, allowing for effective learning and optimization. A key attack on cryptographic ciphers, known as differential cryptanalysis, explicitly exploits how small input differences propagate—an “avalanche effect” that is desirable in ciphers but highly undesirable in robust neural networks.

A fascinating instance of cross-pollination between these fields is the Feistel network, a construction prevalent in cryptography. A Feistel network allows an invertible function to be built using non-invertible components. It takes two inputs, applies a non-invertible function to one, combines it with the other, and then swaps them. By remembering the initial input, the entire operation can be made reversible.

This concept was directly imported into neural networks with the development of “Reversible Networks” (RevNets) in 2017. RevNets make entire neural network layers invertible. The primary benefit of this design for neural networks, particularly during training, is massive memory savings. Instead of storing all activations from the forward pass for use in the backward pass, a reversible network can recompute, or “rematerialize,” these activations on the fly by running the network backward. This trade-off of increased compute for reduced memory is the opposite of the strategy employed for optimizing KV caches, where more memory is used to save compute.

💡 Digging Deeper

Q: How do neural networks and cryptographic protocols, despite having similar architectural patterns, serve inverse functions?
A: Cryptographic protocols aim to scramble information to make it appear random, preventing unauthorized extraction of structure. Neural networks, conversely, take seemingly random or unstructured data and extract meaningful higher-level patterns and structure.

Q: What is a Feistel network and how has it been applied to neural networks?
A: A Feistel network is a cryptographic construction that allows you to build an invertible function using non-invertible components. In neural networks (RevNets), this principle is used to make entire layers invertible. This allows activations to be recomputed during the backward pass instead of being stored, significantly reducing memory usage during training.

Q: What is the main benefit of using a reversible network (RevNet) architecture during training?
A: The primary benefit of RevNets is substantial memory savings during training. By making the network invertible, activations needed for the backward pass can be rematerialized (recomputed) on the fly, eliminating the need to store them all in memory, which is often the largest memory footprint during training.

Key Takeaways

AI inference efficiency is a delicate balance of compute and memory resources. Batching is a crucial strategy to amortize fixed costs, but finding the “Goldilocks zone” between latency and cost requires careful consideration of hardware limits and model architecture. Bottlenecks often shift between memory bandwidth and compute power, especially with varying context lengths, driving the need for sophisticated optimizations.

Scaling models, particularly those employing Mixture-of-Experts, introduces significant communication challenges. While intra-rack communication is highly optimized, inter-rack communication often becomes a bottleneck, dictating the practical limits of how large an MoE layer can be. This fundamental constraint is a key driver behind hardware design efforts to create larger, more densely cabled scale-up domains with increased aggregate memory bandwidth.

Optimization strategies like pipeline parallelism primarily target memory capacity for model weights, but the KV cache remains a persistent memory and bandwidth challenge due to its linear growth with context length and number of active sequences. API pricing models offer a fascinating, albeit indirect, window into these underlying hardware costs, revealing how providers balance different memory tiers and processing modes (prefill vs. decode) to offer competitive and profitable services.

Q&A

Q1: Why are companies like Claude and Codex offering “Fast Mode” at a higher price for faster token streaming?
A: This is primarily due to batch size. To achieve lower latency, models must run smaller batches. This means fixed costs, such as loading model weights, are amortized over fewer tokens, making each token proportionally more expensive to produce.

Q2: How does the KV cache work and why is it important for inference performance?
A: The Key-Value (KV) cache stores internal representations of previously processed tokens (Key and Value vectors). During autoregressive decoding, each new token “attends” to these cached representations, avoiding redundant computations and significantly speeding up inference, though it demands substantial memory bandwidth.

Q3: What role does “sparsity” play in optimizing AI models, especially with Mixture-of-Experts (MoE)?
A: Sparsity in MoE models means that only a fraction of the total experts (parameters) are activated for each token, thereby reducing the computational cost. This strategy allows for potentially larger models with less overall compute, but it often necessitates larger batch sizes and increased memory capacity for efficient operation.

Q4: Why does communication between racks create a bottleneck for large AI models?
A: Inter-rack communication typically relies on a slower “scale-out” network, which can be around eight times slower than the high-speed “scale-up” network used within a single rack. This speed disparity creates a significant bottleneck for the “all-to-all” communication patterns required by Mixture-of-Experts layers when they are distributed across multiple racks.

Q5: How does pipeline parallelism benefit AI inference, and what are its limitations regarding the KV cache?
A: Pipeline parallelism improves AI inference by distributing a model’s layers across multiple compute units, primarily reducing the memory capacity needed per unit for model weights. However, its benefit for the KV cache is limited because the number of in-flight sequences must increase to keep the pipeline busy, which negates the memory savings for the KV cache per GPU.

Q6: What insights can be gained from the API pricing structures of large language models?
A: API pricing often reflects underlying hardware costs and bottlenecks. For example, higher prices for longer context lengths or for decode operations (compared to prefill) can indicate whether the system is memory-bandwidth bound or compute-bound for those specific operations, and how different memory tiers (like HBM, Flash, or even spinning disk) are utilized to manage data retention costs.

Q7: In what surprising way do neural networks and cryptographic protocols share architectural similarities?
A: Both neural networks and cryptographic protocols exhibit convergent evolution in their need to “mix” or “scramble” information across inputs. Cryptographic protocols aim to make data indistinguishable from randomness for security, while neural networks extract meaningful structure from seemingly unstructured data. This commonality even led to concepts like Feistel networks from cryptography being adapted for memory-efficient reversible neural networks (RevNets) in AI.